Nano-Fabrication Techniques for All-Optical Sequential Logic Circuits: A Review

Abstract

To fabricate nanoscale sequential logic circuits, a series of processes to shape, define, and perfect the device geometry must be carefully orchestrated. The aim of this work is to clarify the basic fabrication processes for manufacturing sequences of logic circuits, underscoring actual methodologies in which one can form an exact nanoscale configuration. The process begins with thin-film deposition, including the formation of basic metal or dielectric layers using methods such as physical vapor deposition (PVD) and chemical vapor deposition (CVD). Once the material stack is prepared, circuit geometry is defined by high-resolution patterning techniques, such as e-beam lithography, UV lithography, or nanoimprint lithography. These patterns are then transferred to the deposited films with plasma etchings such as RIE (Reactive Ion Etching) or ICP (Inductively Coupled Plasma) to shape the optical or plasmonic features. In the final stage, state-of-the-art fabrication methods (being, among others, focused ion beam milling, two-photon polymerization, or 3D direct laser writing) are used to fine-tune particular regions or specific complex structures. These combined processes present an easily implemented, versatile fabrication strategy for complex geometries required in plasmonic and photonic sequential logic devices.